About
I am Po-Hsiang Hsu (許博翔), an M.S. student in Electrical Engineering at National Tsing Hua University in Hsinchu, Taiwan. My research focuses on large language models and vision-language models: how they can adapt to domains far from their pretraining data with only a handful of examples, and how LLM agents can take over specialised engineering workflows.
That work has produced two publications: Inductive Visual Logic (ECCV 2026), a training-free framework for few-shot adaptation of VLMs to distant out-of-distribution domains, and MenTeR (IEEE ICLAD 2025), a fully automated multi-agent workflow that turns RF/analog circuit specifications into netlists.
Outside research I build open-source tools: CodefyUI, a visual node-based deep learning pipeline builder for education; all-code, a CLI that configures LLM providers for many coding agents at once; pairmux, tmux terminal primitives for AI agents; and Journey Unfinished, a travel journal website.
Experience
Software Engineer (Contract) · AMD
Remote
HPC system planning and building; development and maintenance of the AMD University Research Learning Cloud.
- HPC
- Proxmox VE
LLM Intern · MediaTek
Hsinchu, Taiwan
Large language model research; co-authored MenTeR, a multi-agent workflow for RF/analog netlist design (IEEE ICLAD 2025).
- Large Language Models
- Python
FPGA Intern · Accton Technology
Hsinchu, Taiwan
- C++
- Python
- FPGA
Education
M.S. in Electrical Engineering · National Tsing Hua University
Hsinchu, Taiwan
Bachelor's degree in Electrical Engineering · National Tsing Hua University
Hsinchu, Taiwan